1. Field of the Invention
The present invention relates to a method and cell for controlling the power factor of a power supply line and, more particularly, to a method for controlling the power factor of a power supply line using a cell for controlling the power factor connected to said power supply line.
2. Description of the Related Art
As is known, the need of a higher and higher power, together with an improved quality of the power itself, has made it necessary to develop circuit topologies capable of providing improved electric performance and advantages also in terms of weight and dimensions.
From the physical point of view, the weight and dimensions of the components of these circuit topologies have been reduced by using applications operating at a higher frequency than the supply frequency (typically 50-60 Hz).
From the electric point of view, performances have been improved mainly in terms of quality of the supplied electric power. In particular, the problem of the harmonic content linked to the use of circuit topologies having components operating at high frequencies has been encountered, such harmonic content being capable of lowering the so-called power factor (PF). Several methods are known that are suitable for increasing the power supplied by the circuits and to reduce the harmonic content in the current of the network whereto these circuits are connected.
One of the known methods provides the use of a circuit network capable of correcting the power factor PF. This network is commonly indicated with the term PFC cell. The main feature of this network is that of creating an input current waveform of the sinusoidal type and in phase with the network voltage.
There are different techniques to obtain this behaviour. One well-known technique exploits the so-called dither effect, and it uses an energy buffer and a high-frequency voltage or current signal (dither signal) to realize a Single Stage Converter (SSC) stage.
In particular, FIG. 1 schematically shows possible configurations of PFC cells using the technique based on the dither effect and inserted between a first T1 and a second network terminal T2. In this FIG. 1, dither signal generators have been indicated with D and buffer elements of the first order of the PFC cells (such as a capacitor or an inductor) with Z.
In particular, this FIG. 1 shows configurations wherein the series of the buffer element Z and of the dither signal generator D is (A) connected to the first network terminal T1, or (B) between the first network terminal T1 and the second network terminal T2 (F), wherein the buffer element Z is inserted between the first network terminal T1 and the second network terminal T2, and the dither signal generator D is connected to the first network terminal T1, or (C) wherein the buffer element Z is connected to the first network terminal T1 and the dither signal generator D is inserted between the first and second network terminals T1, T2, downstream the buffer element Z or, (D) upstream of the buffer element Z, or (E) wherein the buffer element Z and the dither signal generator D are in parallel to each other and connected to the first network terminal T1.
The circuit topologies being shown realize first-order PFC cells and they allow the conduction time of the rectifier diodes to be increased, linearizing the trans-feature of these diodes and increasing therefore the power factor PF of the circuit topology as a whole.
The dither signal is usually obtained by a power stage being cascade-connected to the PFC cell, and by using a stage operating at high frequency the dither signal will also be at high frequency.
By conveniently configuring the PFC cell, the input current can take the waveform of a pulse train, whose envelope reproduces the sinusoidal trend of the network voltage. Finally, by removing high-frequency components, using for example a low-pass filter, a sinusoidal waveform is obtained and thus a high value of the power factor PF.
Besides the dither effect principle, there are other circuit topologies among which the most widespread is that based on the principle commonly known as boost converter.
A typical diagram of a PFC cell based on this principle is schematically shown in FIG. 2. The PFC cell 20 essentially comprises a controlled switch SW. In particular, the PFC cell 20 has a first I1 and a second input terminal I2, as well as a first output terminal O1 and a second output terminal O2.
The first input terminal I1 is connected to the first output terminal O1 by means of the series of an inductor L and a diode D, connected to each other in correspondence with an internal circuit node X.
The second input terminal I2 is directly connected to the second output terminal O2.
The controlled switch SW is inserted between the internal circuit node X and the second input terminal I2, i.e., the second output terminal O2, and it has a driving terminal connected to a convenient driving circuit 22.
The PFC cell 20 is connected to the first network terminal T1 and a second network terminal T2 by means of a diode bridge 21. In particular, the diode bridge 21 comprises a first pair of diodes D1, D2 inserted between the first input terminal I1 and the second input terminal I2 of the PFC cell 20 and interconnected in correspondence with the first network terminal T1, as well as a second pair of diodes D3, D4 inserted, in parallel to the first pair of diodes D1, D2, between the first input terminal I1 and the second input terminal I2 and interconnected in correspondence with the second network terminal T2. The diode bridge 21 comprising the pairs of diodes D1-D2 and D3-D4 operates as an input rectifier bridge.
The PFC cell 20 also has the input terminals I1, I2 and the output terminals O1, O2 connected to a first C1 and a second capacitor C2 respectively. The PFC cell 10 is finally connected to a load Z inserted between the output terminals O1 and O2.
The combination of the capacitor C2 and of the PFC cell 20 substantially realizes an active filter driven by the driving circuit 22 and capable of controlling the harmonic content of the power absorbed by the load. In most cases, the switch SW is an electronic switch realized with an active component of the MOSFET type, driven by the integrated IC driving circuit 22 so as to adjust the conduction time thereof.
Nevertheless, the use of an integrated circuit IC for driving the electronic switch makes the circuit topology of the PFC cell 20 shown in FIG. 2 expensive and thus suitable for products of the high market range.